The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to an improvement in isolating elements of a MOSLSI (Metal Oxide Semiconductor Large Scale Integrated Circuit).
Heretofore, a selective oxidation method has been in general employed as an interelement isolating method in the step of manufacturing a semiconductor device and particularly an MOSLSI. This method will be described in more detail using an n-channel MOSLSI as an example.
As shown in FIG. 1(A), an SiO.sub.2 film 2 is first grown by thermal oxidation on a p-type Si substrate 1 having a crystal plane (100), and an Si.sub.3 N.sub.4 film 3 is accumulated on the film 2. Subsequently, a resist film 4 is formed by a photoetching method on an element forming portion. With the film 4 as a mask, the film 3 except the element forming portion is etched and removed, and an Si.sub.3 N.sub.4 pattern 3' is formed. Then, a boron ion implantation is, for example, performed, thereby forming a p.sup.+ type region 5 as a channel stopper region in the field region (FIG. 1(B)). After the film 4 is removed, a wet oxidation is carried out with the pattern 3' being employed as a mask, and a thick field oxidized film (field region) 6 is selectively grown (FIG. 1 (C)). Subsequently, the pattern 3' and the film 2 are etched and removed, thereby forming an element forming region 7 isolated between field regions 6 (FIG. 1(D)). Thereafter, as shown in FIG. 1(E), a gate electrode 9 formed of a polycrystalline silicon is formed through a gate oxidized film 8 on the region 7, and arsenic is, for example, diffused in the region 7 to form n.sup.+ regions 10 and 11 as a source and a drain. A CVD-SiO.sub.2 film 12 are eventually accumulated as an interlayer insulating film on the overall surface. Contacting holes 13 are opened at the portions corresponding to the regions 10 and 11, and the gate electrode 9 over the film 8, and aluminum wires 14 are formed in film 12, thereby manufacturing an n-channel MOSLSI (FIG. 1(F)).
The above-described conventional selective oxidation method of manufacturing the MOSLSI, however, has various drawbacks as described below.
FIG. 2 shows in detail a sectional structure of the MOSLSI in which the field region 6 is formed with the pattern 3' shown in FIG. 1(C) as a mask. It is in general known that the region 6 intrudes into the region under the pattern 3' when growing by the selective oxidation method (a region F in FIG. 2). In this case, the region F consists of a portion D or a so-called "bird's beak" where an oxidizer is diffused through the thin film 2 under the pattern 3' during the field oxidation, and a portion E where the thick part of the region 6 is laterally intruded. When the region 6 is 1 .mu.m in thickness for example, and is grown under the conditions that the thickness of the pattern 3' is 1,000 .ANG. and the film 2 under the pattern 3' is 1,000 .ANG. thick, the length of the portion F reaches approximately 1 .mu.m. It is assumed that a distance A between the patterns 3' is 2 .mu.m. Then, the width C of the field region cannot be reduced to less than 4 .mu.m, since the width of the portion F is 1 .mu.m, resulting in a large obstruction in the integration of an LSI. Thus, a method of suppressing a bird's beak (the portion D in FIG. 2) by reducing the thickness of the film 2 under the pattern 3' use of a thick pattern 3' and a method of suppressing the intruded portion F of the field by reducing the thickness of the grown film of the field 6 have been recently proposed. However, the former causes a large stress at the end of the field, resulting in the ready production of defects, and the latter has a problem of a decrease in the inverted voltage of the field. In this manner, there is a limit to the integration of an LSI by the conventional selective oxidation method.
When a channel stopper is provided, boron ions implanted as the channel stopper diffuses laterally during a field oxidation. As shown in FIG. 3(A), part of the region 7 becomes the region 5, and the effective element region is narrowed from the width G to the width H. As a result, a narrow channel effect such as a reduction in the current of a transistor or an increase in the threshold voltage occurs when microminiaturization of an element is carried out. Since the region 5 extends further laterally, a junction between the region 11 (or 10) and the region (5) in the region 7 becomes wide as shown in FIG. 3(B), resulting in an increase in the floating capacitance between the regions 10, 11 and the substrate 1. This capacitance cannot be ignored as the element is reduced.
Further, the conventional element isolating method has the following drawbacks.
As shown in FIG. 4(A), since the region 6 and the electrode 9 are not self-aligned, it is necessary to provide an alignment margin portion 15 in the region 6 to enable the electrode 9 to extend into the region 6. This structure obstructs the integration of the LSI. More particularly, as shown in FIG. 4(B), it is necessary to form a spacing I (which depends upon the minimum size of a photoetching method) between gate electrodes 9.sub.1 and 9.sub.2, in addition to margins J and K of the portions 15.sub.1 and 15.sub.2, so that different electrodes 9.sub.1 and 9.sub.2 face each other on the region 6. It is assumed that the relationship of the lengths of the margins J and K and the spacing I is J=K=I=1 .mu.m. Then, the minimum width M of the region 6 in this portion should become 3 .mu.m. Thus, it is impossible to form the field region having a width less than this length.